• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
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    • 专利摘要:
    "screens with additional load structures". The present invention relates to a screen that may have a pixel matrix, such as liquid crystal display pixels. The screen may include rows of short pixels that extend only partially across the screen and rows of full-width pixels that span the width of the screen. Door lines coupled with rows of short pixels may extend into the idle area of the screen. door line supplemental load structures may be situated in the idle area of the screen to increase the load on door lines that are coupled to rows of short pixels. gate line overhead structures may include doped polysilicon and data lines overlapping the door lines in the inactive area. On screens that combine display and touch functionality in a thin-film transistor layer, supplemental load structures can be used in the idle area to increase the load on common voltage lines that are coupled with short rows of common voltage blocks.
    公开号:BR102018016260A2
    申请号:R102018016260-8
    申请日:2018-08-09
    公开日:2019-03-26
    发明作者:Shin-Hung Yeh；Abbas Jamshidi Roudbari；Ting-Kuo Chang
    申请人:Apple Inc.；
    IPC主号:
    专利说明:

    Descriptive Report of the Invention Patent for SCREENS WITH SUPPLEMENTARY LOAD STRUCTURES.
    [0001] This application claims priority over US patent application No. 15 / 980,437, filed on May 15, 2018, and US provisional patent application No. 62 / 555,457, filed on September 7, 2017, which are hereby incorporated by reference in their entirety.
    BACKGROUND OF THE INVENTION [0002] The present disclosure relates generally to electronic devices, and, more particularly, to electronic devices with screens.
    [0003] Electronic devices such as cell phones, computers and other electronic devices often contain screens. A screen includes an array of pixels to display images to a user. The screen trigger circuit, like a data line trigger circuit, can provide data signals to the pixel array. The door line driver circuit in the screen driver circuit can be used to set a door line signal in each row of pixels on the screen to the active state in sequence to load data into the pixels.
    [0004] Brightness variations can also arise due to control problems in screens with non-rectangular shapes. If due care is not taken, effects like these can adversely affect the performance of the display.
    SUMMARY OF THE INVENTION [0005] A screen can have an array of pixels, such as liquid crystal screen pixels controlled by the screen trigger circuit. The screen trigger circuit can provide pixels with data signals over rows of data in pixels columns and can provide pixels with port line signals over the rows of pixels in rows of pixels. CirPetição 870180069131, of 08/09/2018, p. 8/104
    2/32 the door trigger on the screen trigger circuit can be used to provide the door line signals.
    [0006] The door trigger circuit may have door trigger circuits, each of which provides a respective signal among the signals from the door lines to the pixels in a respective row of the pixel matrix.
    [0007] Different rows on a screen can have different numbers of pixels and can therefore be characterized by different amounts of capacitive charge. To ensure uniformity of brightness for the screen, a screen can be provided with additional load structures of row-dependent door line.
    [0008] The door lines attached to the rows of short pixels can extend into the idle area of the screen. The door line overhead structures can be located in the idle area of the screen to increase the load on the door lines that are coupled to the rows of short pixels. Door line overhead structures can include data lines and doped polysilicon that overlap door lines in the idle area.
    [0009] The doped polysilicon can be coupled to a polarizing voltage supply line, such as a ground line or other signal line. A transparent conductive layer as an extension of a common electrode voltage layer can be used in the idle area of the screen to couple the polysilicon to the bias voltage supply line. In other arrangements, a metal layer can be used to couple the polysilicon to the bias voltage supply line. The metal layer can be formed from the same material that forms the data lines in the active area of the screen.
    [0010] On screens that combine display and touch functionality in a thin film transistor layer, supplementary load structures can be used in the idle area to increase the load
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    3/32 on common voltage lines that are coupled to short rows of common voltage blocks. The additional charge structures can include transparent conductive electrodes that, respectively, overlap the voltage blocks common in the inactive area. The transparent conductive electrodes can be formed from the same material as the pixel electrodes in the active area of the screen. Transparent conductive electrodes and common voltage blocks form capacitors that increase the capacitive load on common voltage lines that are coupled to short rows of common voltage blocks. BRIEF DESCRIPTION OF THE DRAWINGS [0011] Figure 1 is a schematic diagram of an illustrative electronic device that has a screen according to a modality.
    [0012] Figure 2 is a top view of an illustrative screen on an electronic device according to a modality.
    [0013] Figure 3 is a circuit diagram of an illustrative pixel circuit on a screen according to a modality.
    [0014] Figure 4 is a cross-sectional side view of an illustrative screen showing the locations of the illustrative thin film layers according to an embodiment.
    [0015] Figure 5 is a diagram of an illustrative screen that has a pixel-free notch along its upper edge and that can have rows of short pixels and rows of full-width pixels according to a modality.
    [0016] Figure 6 is a graph showing how the door line load can be adjusted as a function of the row position on a screen to help minimize variations in screen brightness according to a modality.
    [0017] Figure 7 is a top view of a portion of an illustrative screen showing how line overhead structures
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    4/32 door, like dummy pixel structures, can be added to the rows on a screen to match brightness variations according to a modality.
    [0018] Figure 8 is a top view of a portion of an illustrative screen showing how data line extensions and polysilicon load structures can be used to increase the port line load according to a modality.
    [0019] Figure 9 is a side view in cross section of the screen in Figure 8 showing how the polysilicon charge structures can be polarized using a common voltage electrode layer according to one modality.
    [0020] Figure 10 is a top view of a portion of an illustrative screen showing how adjacent pairs of door lines can have separate polysilicon loading structures according to one embodiment.
    [0021] Figure 11 is a top view of a portion of an illustrative screen showing how a pair of door lines can have polysilicon loading structures coupled according to one embodiment. [0022] Figure 12 is a top view of an illustrative screen that shows how an earth circuit can be formed from segments of different layers of metal, according to one modality.
    [0023] Figure 13 is a top view of an illustrative screen that shows how the polysilicon load structures can be polarized using a low voltage gate line according to one modality.
    [0024] Figure 14 is a side view in cross section of the screen in Figure 13, showing how a low voltage gate line can be electrically coupled to a polysilicon load structure according to one modality.
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    5/32 [0025] Figure 15 is a top view of an illustrative screen that shows how supplementary charge structures can be used to increase the load on signal lines that are coupled to short rows of common electrode blocks accordingly with a modality. [0026] Figure 16 is a top view of the screen in Figure 15 showing how polysilicon charge structures can be used to increase charge on door lines in rows of short pixels and transparent electrode charge structures can be used. to increase the charge in short rows of common electrode blocks according to one modality.
    DETAILED DESCRIPTION [0027] An illustrative electronic device of the type that can be supplied with a screen is shown in Figure 1. The electronic device 10 in Figure 1 can be a tablet computer, a laptop computer, a desktop computer, a monitor that includes a built-in computer, a monitor that does not include a built-in computer, a monitor for use with a computer or other equipment external to the screen, a cell phone, a media player, a wristwatch device, or other electronic equipment used with the body, or other suitable electronic device.
    [0028] As shown in Figure 1, electronic device 10 may have a control circuit 16. Control circuit 16 may include storage and processing circuits to support the operation of device 10. The storage and processing circuit may include storage. such as hard disk storage, non-volatile memory (eg flash memory or other electrically programmable read-only memory configured to form a solid state drive), volatile memory (eg static or dynamic random access memory) etc. . The processing circuit in control circuit 16 can be used to control
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    6/32 control the operation of the device 10. The processing circuit can be based on one or more microprocessors, microcontrollers, digital signal processors, baseband processors, power management units, audio chips, integrated circuits for specific application etc.
    [0029] The input and output circuit on device 10, as input and output devices 12, can be used to allow data to be provided to device 10 and to allow data to be provided from device 10 to external devices. Input and output devices 12 can include buttons, joysticks, scroll wheels, touch sensitive surfaces (touch pads), keypads, keyboards, microphones, speakers, tone generators, vibrators, cameras, sensors, light emitting diodes light and other status indicators, data ports etc. A user can control the operation of the device 10 by providing commands via the input and output devices 12, and can receive status information and other outputs from the device 10 using the output features of the input and output devices 12.
    [0030] Input and output devices 12 can include one or more screens, such as screen 14. Screen 14 can be a touchscreen that includes a touch sensor to detect a user's touch input or screen 14 can be insensitive to touch. A touch sensor for screen 14 can be based on an array of capacitive touch sensor electrodes, acoustic touch sensor structures, resistive touch components, force-based touch sensor structures, a light-based touch sensor , or other suitable touch sensor arrangements.
    [0031] Control circuit 16 can be used to run software on device 10, such as an operating system and application code. During operation of device 10, the software
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    7/32 executed on the control circuit 16 can display images on screen 14 using a matrix of pixels on screen 14.
    [0032] Screen 14 can be a light emitting organic diode screen, a liquid crystal screen, an electrophoretic screen, an electro-humidification screen, a screen based on a set of different crystalline light emitting diode arrays, or a screen based on other types of display technology. The configurations in which the screen 14 is a liquid crystal display can sometimes be described here as an example.
    [0033] The screen 14 can have a rectangular shape (that is, the screen 14 can have a rectangular projection area and a rectangular peripheral edge that extends around the rectangular projection area,) or it can have other suitable shapes. The screen 14 can be flat or it can have a curved profile.
    [0034] Figure 2 shows a top view of a portion of the screen
    14. As shown in Figure 2, the screen 14 can have a pixel array 22 formed from substrate structures like substrate 36. Substrates like substrate 36 can be formed from glass, metal, plastic, ceramic or others substrate materials. Pixels 22 can receive data signals via signal paths like D data lines and can receive one or more control signals via control signal paths like horizontal G control lines (sometimes called gate lines, lines scan lines, emission control lines, door signal paths, etc.). There may be any suitable number of rows and columns of pixels 22 on screen 14 (e.g., tens or more, hundreds or more, or thousands or more). In organic light-emitting diode screens, pixels 22 contain respective light-emitting diodes and pixel circuits that control the application of current to the light-emitting diodes. On liquid crystal displays, pixels 22 contain pixel circuits
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    8/32 that control the application of signals to pixel electrodes that are used to apply controlled amounts of electric field to pixel size portions of a liquid crystal layer. The pixel circuits in pixels 22 can contain transistors that have ports that are controlled by port line signals on the G port lines. [0035] Screen trigger circuit 20 can be used to control the operation of pixels 22. The circuit Screen driver 20 can be formed from integrated circuits, thin film transistor circuits, or other suitable circuits. Thin-film transistor circuits can be formed from polysilicon thin-film transistors, semiconductor oxide thin-film transistors, such as indium gallium zinc oxide transistors, or thin-film transistors formed from other semiconductors . Pixels 22 may have color filter elements or other colored structures of different colors (for example, red, green and blue) to provide screen 14 with the ability to display color images.
    [0036] The screen trigger circuit 20 may include screen trigger circuits such as the screen trigger circuit 20A and the door trigger circuit 20B. The screen driver circuit 20A can be formed from one or more screen driver integrated circuits and / or thin film transistor circuits (for example, timing controller integrated circuits). The door drive circuit 20B can be formed from door drive integrated circuits or it can be a thin film matrix door circuit. The screen trigger circuit 20A of Figure 2 can contain communication circuits for communication with the control circuit of the system, like the control circuit 16 of Figure 1, through path 32. Path 32 can be formed from tracks in a flexible printed circuit or other conductive lines. During operation, the control circuit (for example, control circuit 16 in Figure 1) can be
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    9/32 provide circuit 20A with information about the images to be displayed on screen 14.
    [0037] To display images in display pixels 22, the screen trigger circuit 20A can provide image data to data lines D while emitting control signals to support the screen trigger circuit, such as a door trigger circuit 20B on the path 38. Path 38 may, for example, include lines to carry power signals as a Vgh gate high voltage signal (which can serve as a maximum gate line signal value emitted from the gate drive circuit over each port) and a low voltage Vgl port signal (which can serve as a ground), control signals such as port output enable signals, clock signals, etc. Circuit 20A can supply these signals to door trigger circuit 20B on one or both edges of screen 14 (see, for example, path 38 'and door trigger circuit 20B' on the right side of screen 14 in the example in Figure 2).
    [0038] The 20B gate drive circuit (sometimes called the horizontal control line control circuit) can control horizontal control lines (gate lines) G using the signals received from path 38 (for example, using the high door voltage, low door voltage, door exit enable signals, door clock signals, etc.). The gate lines G on the screen 14 can each carry a gate line signal to control the pixels 22 of a respective row (for example, to activate transistors on the pixels 22 when loading data from the data lines into capacitors of storage in those pixels of data lines D). During operation, image data frames can be displayed by setting a door signal on each G port line on the screen to the active state in sequence. The shift register circuit (for example, a chain of door trigger circuits
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    10/32 formed from registers and associated output buffers) on the door trigger circuit 20B can be used to control the door line signals.
    [0039] Figure 3 shows an illustrative pixel circuit for pixels 22 of screen 14. As shown in Figure 3, each pixel 22 can include a pixel size portion of an LC liquid crystal layer, which can be supplied electric fields with the use of corresponding pixel electrodes. The magnitude of the applied field is proportional to the pixel voltage Vp minus the common electrode voltage Vcom. During data load operations, a desired data line signal (ie, a data voltage Vp that must be loaded at pixel 22) is routed to data line D. The port line signal on the data line port G is set to the active state while the data line signal on data line D is valid. When the gate line signal is set to the active state, the gate of transistor T is raised and transistor T is activated. With the transistor T activated, the data from line D is directed to the storage capacitor Cst and establish the pixel voltage Vp. The storage capacitor Cst maintains the value of Vp between successive image frames.
    [0040] Figure 4 shows a side view in cross section of a portion of the active area of screen 14. In region 30, screen 14 may have a backlight unit that generates backlight illumination. Backlight illumination passes through the thin film transistor circuit 34 (sometimes called the thin film transistor layer), which forms a matrix of pixels 22. In region 54, screen 14 may include a color filter layer and a liquid crystal layer interposed between the color filter layer and the thin film circuit 34. Layers 54 and the thin film transistor circuit 34 can be sandwiched between upper and lower polarizers.
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    11/32 [0041] The thin film transistor circuit 34 can include a substrate layer like substrate 36. Substrate 36 can be formed from clear glass, plastic, or other materials. The light shield structure 202 can be formed under thin film transistors like the illustrative transistor 56. The light shielding structure 202 can be formed from metal (for example). The dielectric buffer layer (s) 66 can be formed on the substrate 36. The thin film transistor circuit 34 can also include dielectric layers such as the insulating layer of gate 64 and interlayer dielectric layers 206 and 218. Dielectric layers, such as layers 66, 64, 206 and 218, can be formed from silicon oxide, silicon nitride, other inorganic materials, or other insulators. Dielectric planarization layers, such as layers 208 and 214, can be formed from organic layers (for example, polymers) or other insulators.
    [0042] Conductive layers, such as layers 216 and 220, can be formed from tin and indium oxide (ITO) or other transparent conductive material. Layer 220 can be provided with a pattern to form electrode fingers for a pixel electrode driven by the thin film transistor 56. Layer 220 can be separated from a common voltage layer (Vcom) formed from layer 216 by the layer interlayer dielectric 218. Transistor 56 may have a channel formed from polysilicon layer 204, gate and source terminals formed from metal layer 60, and a port formed from metal layer 222 (which is separated of the channel by the door insulator 64). The intermediate metal layer 210 can be interposed between the interlayer dielectric layer 206 and the planarization layer 208, and can be used to form signal interconnections. Other screen structures can be formed using the layers in Figure 4 and / or different thin film layers
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    12/32 can be included on screen 14. The thin film structures in Figure 4 are for illustrative purposes only.
    [0043] In configurations for the device 10 in which the screen 14 has the same number of pixels 22 in each row of the screen 14, the capacitive load in the port lines of the screen 14 will be relatively uniform throughout all the rows of the screen 14 In other configurations for screen 14, such as the illustrative configuration in Figure 5, different rows of screen 14 may contain different numbers of pixels 22. This can give rise to a row-dependent capacitive load on the door lines (for example, door lines carrying signals such as a high voltage Vgh port signal and a low voltage Vhl port signal) which can affect the brightness resulting from the light in the 22 pixels of each row.
    [0044] In the illustrative arrangement of Figure 5, screen 14 has a rectangular shape with four curved corners and a recess (that is, notched region free of pixels 66). The notch breaks the rows of pixels 22 and creates short rows that have fewer pixels than the rows of normal length that span the width of the screen substrate 14. Due to the curved corners of the screen 14, each row at the top and bottom edges of the screen 14 will have a slightly different amount of capacitive charge. Due to the gradually curved shape of the peripheral edge of the screen 14 at the top and bottom edges of the screen 14, the change from row to row in the number of pixels 22 that carry the door lines will be gradual in these regions. As a result, variations in luminance due to changes in row length (and therefore pixel count) between adjacent rows will be minimal and not noticeable to a screen observer 14.
    [0045] More abrupt format changes, such as changes in screen 14 due to notch 66, will introduce more significant changes in the pixel load on the door lines. Rows like the rows
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    RM + 1 ... RN on screen 14 of Figure 5 (sometimes called full-width pixel rows) have pixel counts that are the same (or, in the case of the rows on the bottom edge of the screen 14, are almost equal) ) each other. Rows like the R0 ... RM rows (sometimes called short pixel rows) will have pixel counts that are smaller than the pixel counts of the RM + 1 ... RN rows. This is due to the fact that the pixels in rows R0 ... RM will extend only to the left and right contours of region 66.
    [0046] Due to the fact that the door lines in area A of screen 14 (that is, the door lines of rows R0 ... RM at the top edge of screen 14 adjacent to region 66) and the door lines in area B of screen 14 (that is, the door lines of rows RM + 1 ... RN) experience different amounts of charge in the example in Figure 5, there is a risk that pixels 22 in areas A and B are loaded with different voltages in your Cst storage capacitors, even in the presence of identical Vp values in your data lines. The port line load affects the shape of the port line pulses in the port lines and can therefore affect the brightness of the pixels. Door lines with larger amounts of door line load will tend to be more attenuated than door lines with smaller amounts of door line load. The rows on screen 14 can be provided with different amounts of door line load to help reduce brightness variations. As an example, shorter rows that have fewer pixels may be provided with extra charges (sometimes called dummy loads, dummy pixels or overhead door line load structures) to help make those rows behave in a way similarly or identically to longer rows on the screen.
    [0047] Figure 6 shows a graph illustrating the impact of various loading schemes that can be used to help smooth out
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    14/32 brightness variations on a screen that has rows of pixels of uneven lengths (different numbers of pixels). In the example in Figure 6, the port line load (LOAD) was plotted as a function of the row number (for example, for the top portion of the screen 14 starting at row R0 in Figure 5). Solid line 190 corresponds to a screen that has the shape shown in Figure 5, but without any additional load structures. The rows from R0 to RM (ie, the rows in area A of Figure 5) experience gradually increasing amounts of charge. From row RM + 1 to row RN (that is, in area B), the load reaches the load value LM. With a non-compensated screen configuration (solid line 190), there can be a relatively sharp discontinuity (DLM load difference) in the amount of load experienced by the port lines of the respective RM rows and the RM + 1 row. This discontinuity can lead to a noticeable variation between the brightness of the pixels in the RM row and the brightness of the pixels in the RM + 1 row.
    [0048] Brightness variations such as these can be smoothed by adding additional door line load structures to the appropriate rows of screen 14. With an illustrative arrangement, which is illustrated by line 192, the door line load is smoothed by addition of additional loads to the door lines of rows 198. If desired, additional smoothing can be achieved (for example, by adding varying amounts of load to each of the door lines of the rows from R0 to RM, as illustrated by line 194). If desired, the door lines in the rows from R0 to RM can be compensated by adding an additional charge of the door line sufficient to equalize the load on the door lines of all the rows on screen 14 (see, for example, illustrative load line 196 of Figure 6). In general, any suitable amount of supplemental charge can be added to suitable rows of screen 14. Loads
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    Supplementary 15/32 can be significant (for example, to completely equalize the load for all lines as illustrated by line 196), can be moderate (for example, to smooth a load as shown by line 194), or can be relatively small (for example, to help smooth the discontinuity of charge in the RM / RM + 1 rows by adding charge to a relatively modest number of rows (for example, rows 198), as illustrated by line 192. Any of these schemes also can be combined with row-dependent port signal formatting schemes to help smooth out brightness discontinuities. [0049] Illustrative arrangements for adding additional charges to shorter rows of pixels on screen 14 are shown in Figures 7 through 16.
    [0050] As shown in the illustrative configuration of Figure 7, the screen 14 can have an active region as the active region 40 (that is, the active area AA within the contour line 40) where pixels 22 are located. Screen 14 may also have a pixel-free notch region such as region 66 outside active area 40 that is free of light-emitting pixels 22. Screen 14 may have one or more layers of substrate such as substrate 36. The substrate 36 can have an edge like edge 48. Edge 48 can be straight or curved (as in the example in Figure 7).
    [0051] The door lines of the rows of pixels from R0 to RM can extend along the active area 40 and along the notch region 66 (sometimes called the inactive area or inactive notch region of the screen 14). The pitch of the G gate lines in the inactive region 66 can be less than the pitch of the G gate lines within the active area 40. The reduced pitch of the G gate lines in the inactive region 66 provides a space like space 42 on the screen 14. Space 42 can be used to accommodate one or more electronic components (for example,
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    16/32 input and output components such as a camera, a speaker, an ambient light sensor, a proximity sensor and / or other input and output components).
    [0052] The selected G port lines (for example, the port lines in the rows of pixels from R0 to RM or other suitable port lines) can be coupled to overhead structures (overhead door line structures) such as dummy 22D pixels in slot region 66. Any suitable number of rows of pixels can be supplied with an extra charge (for example, 2 to 20 rows, 2 to 100 rows, 50 to 1,000 rows, more than 25 rows, less than 2000 rows, etc.). Any suitable number of fictitious 22D pixels (for example, 1 to 1,000, more than 10, less than 500, etc.) can be coupled to port line G in each row of screen 14 and / or can be coupled to other lines horizontal control panels on screen 14 to reduce row-dependent brightness variations.
    [0053] The fictitious pixels 22D may contain all or some of the pixel circuits of regular pixels 22 with modifications that prevent these pixels from emitting light. Examples of modifications that can be made to convert active pixels 22 into dummy pixels 22D include: omitting the 22 pixel liquid crystal material from the 22D pixels, omitting the 22D pixel anodes, omitting small portions of metal tracks to create open circuits, etc. The projection area (outline when viewed from above) of each of the 22D pixels in Figure 7 can be the same as the projection area of each of the 22 pixels, or pixels 22 and dummy pixels 22D can have areas different projection
    [0054] If desired, additional charge structures are formed from one or more capacitors in region 66. This type of arrangement is shown in Figure 8. Figure 8 is a top view of
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    17/32 illustrative overhead structures that can be used in the groove region 66 of Figure 6. In this example, overhead structures 22D include DE data line extensions (for example, portions of D data lines in Figure 7 extending into the groove region 66) and the conductive layer 50. A first set of capacitors can be formed in overlapping areas between the DE data line extensions and the G port lines (for example, the DE data line can form a first electrode on each capacitor and port gate lines G can form a second electrode on each capacitor). A second set of capacitors can be formed in overlapping areas between the conductive layer 50 and the gate lines G (for example, the conductive layer 50 can form a first electrode in each capacitor and the gate lines G can form a second electrode each capacitor). One or more dielectric layers can separate the G port lines from the DE data line extensions and the conductive layer 50.
    [0055] The dielectric material between the DE data line extensions and the G port lines and between the conductive layer 50 and the G port lines can be formed from one or more layers of inorganic and / or organic dielectric material on screen 14. Conductive layer 50 can be formed from metal layers, conductive semiconductor layers (e.g., doped polysilicon, etc.) or other conductive layers. For example, conductive layer 50 can be formed from conductive layers such as a first layer of door metal, a second layer of door metal, a source drain metal layer, a silicon layer, or other conductive layers the thin film transistor circuit of screen 14. In an illustrative arrangement, which is sometimes described here as an example, conductive layer 50 can be formed
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    18/32 from a doped polysilicon layer, such as the doped polysilicon layer 204 of Figure 4.
    [0056] If desired, the amount of overlap between the DE data line extensions and the G port lines in each dummy 22D pixel can correspond to the amount of overlap between the D data lines and the G port lines in the pixels light emitters 22. This ensures that DE data line extensions provide port G lines in the inactive region 66 with a capacitive load equal to or similar to that which D data lines provide to port G lines in the active area 40 of the screen 14. Similarly, the amount of overlap between conductive layer 50 (for example, a doped polysilicon layer) and port lines G in dummy pixels 22D may correspond to the amount of overlap between polysilicon layer 204 and lines of G port in pixels 22. This ensures that the polysilicon layer 50 provides the G port lines in the inactive region 66 with a capacitive charge equal to or similar to that of the polysilicon layer 204 in the p ixels 22 provides port G lines in the active region 40 of screen 14.
    [0057] The polysilicon layer 50 in the inactive region 66 can be formed from the same layer of material that forms the polysilicon layer 204 in the active region 40, but the polysilicon layer 50 can be electrically isolated from the polysilicon layer 204. Thus, to provide adequate tension to the polysilicon layer 50, the polysilicon layer 50 can be coupled to a polarizing voltage supply line, such as a ground line (for example, the ground line 38-2) or another signal line (for example, the low voltage signal line 38-1 of port Vgl).
    [0058] In an illustrative arrangement, vertical interconnection routes such as tracks 52 can be used to couple the polysilicon layer 50 to a common voltage layer (Vcom). The Vcom layer
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    19/32 can in turn be coupled to the earth line 38-2 to provide the polysilicon layer 50 with the appropriate polarization voltage.
    [0059] In the example in Figure 8, each 22D overhead load structure has an H shape and is used to increase the load on two adjacent G port lines. The upper half of each H 22D-shaped load structure (for example, the two vertical portions that extend parallel to the y-axis of Figure 8) crosses a first line of door G in two locations, and the lower half of each structure H-shaped load bearing 22D (which also extends parallel to the y-axis of Figure 8) crosses a second door line in two locations. The horizontal portion of each H-shaped load structure (for example, the segment extending parallel to the x-axis of Figure 8) is coupled to path 52 to polarize polysilicon 50 in each load structure 22D.
    [0060] Figure 9 shows a cross section of the overhead load structure 22D of Figure 8 taken along line 68 and seen in direction 70. As shown in Figure 9, the polysilicon layer 50 can be located on top of the buffer layers 66 on the substrate 36. The door insulator 64 can be formed on the buffer layer 66. Door lines G (for example, formed from the metal layer 222 of Figure 4) can be formed on the door insulator 64. The interlayer dielectric layer 206 and the planarization layers 208 and 214 can be formed over the G-door lines. A conductive layer like conductive layer 58 can be formed over the dielectric layers 206, 208 and 214. The conductive layer 58 it can be formed from the same layer of transparent conductive material that forms the common electrode layer in pixels 22 (for example, layer 58 can be formed from ITO 216 of Figure 4). As the conductive layer 58 is formed from the same layer as the common electrode 216 of the active area 40, the bed
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    20/32 of the 58 is sometimes called the common voltage layer (Vcom). However, layer 58 does not need to be electrically coupled to the Vcom layer of pixels 22. Instead, layer 58 can be electrically isolated from the Vcom layer of pixels 22 and can be coupled to a ground line (for example, the land line 38-2 in Figure 8).
    [0061] Door insulator 64 and dielectric layers 206, 208 and 214 can include openings for pathways 52. For example, as shown in Figure 9, layers 64, 206, 208 and 214 include an opening that aligns with the polysilicon layer 50 to allow the track 52 to electrically couple the common electrode layer 58 to the polysilicon layer 50. This allows the common electrode layer 58 to provide a bias voltage to the polysilicon layer 50. If desired, a Optional metal layer, such as metal layer 60, can be electrically coupled between the polysilicon layer 50 and the common stress layer 58.
    [0062] The example in Figure 8 in which the overhead load structures 22D are coupled to the adjacent load structures 22D in the same column is merely illustrative (for example, in which the vertical polysilicon portions 50 extend continuously parallel to the x-axis at the multiple load structures 22D). If desired, polysilicon 50 in each load structure 22D can be isolated from polysilicon 50 in adjacent load structures 22D. This type of arrangement is illustrated in Figure 10. As shown in Figure 10, polysilicon 50 has an H shape on each load structure 22D, but is not connected to adjacent polysilicon 50 in the next row or column of load structures 22D.
    [0063] Figure 11 illustrates an example in which the horizontal polysilicon portions 50 extend continuously across multiple load structures 22D in the same row. Load structures
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    22D in the same column can be separated from each other (as shown in the example in Figure 10) or can be coupled together (as shown in the example in Figure 8).
    [0064] In arrangements in which the fictitious polysilicon layer 50 is polarized using an earth circuit such as earth circuit 38-2, it may be desirable to form the earth circuit from multiple layers of metal to prevent damage to dummy 22D load structures during manufacturing. If the earth circuit 38-2 is formed entirely from a metal layer like metal 222, this could cause the polysilicon 50 to absorb electrical charge while the other layers in the screen 14 are formed, which, in turn, is formed , could damage the 22D load structures. To prevent excess electrical charge from being absorbed by polysilicon 50, the earth circuit 38-2 can be formed from alternating segments of different layers of metal. This type is shown in Figure 12.
    [0065] As shown in Figure 12, the earth circuit 38-2 can be formed from alternating segments of different metal layers like M1 (for example, layer 222 in Figure 4) and M2 (for example, layer 60 of Figure 4). During manufacture, the M1 layer can be deposited and provided with a pattern to form distinct segments. The segments can be separated from each other so as not to form a complete circuit. The metal layer M1 can be divided into two, three, four or more than four separate segments. A second metal layer such as an M2 metal layer can be used to complete the circuit. The second layer of metal M2 and the first layer of metal M1 can be coupled together at locations 72 to form a continuous conductive circuit. A portion of the earth circuit 38-2 can be coupled to the common voltage layer 58 (for example, the portion of the Vcom 216 layer that is formed in the inactive area 66), which is in turn coupled to the po
    Petition 870180069131, of 08/09/2018, p. 10/284
    22/32 lysilicon 50 to polarize the polysilicon 50 at the desired voltage. The example in Figure 12 in which the earth circuit 38-2 is formed from the metal layers M1 and M2 is merely illustrative. If desired, other metal layers such as the metal layer M3 can be used to form the 38-2 earth circuit (for example, the metal layer M3 can be used in place of M2, or can be used in addition to layers M1 and M2 to form the earth circuit 38-2).
    [0066] The example of Figures 8 and 9 in which the common stress layer 58 (for example, a conductive layer in the inactive region 66 which is formed from the same layer as the layer of Vcom 216 in Figure 4, but which is electrically isolated from the Vcom layer in the active area 40 of the screen 14) is used to polarize the polysilicon 50 in the region 66 is merely illustrative. If desired, other conductive layers of the screen 14 can be used to polarize polysilicon 50. Figure 13 illustrates an example in which polysilicon 50 is polarized using an extended portion of signal line 38-1 (for example, a line of gate voltage).
    [0067] As shown in Figure 13, the port low voltage line 38-1 may have vertical segments (for example, segments extending parallel to the y axis of Figure 13) as the vertical segment 38-1 '. The vertical segments 38-1 'can extend along multiple rows of dummy load structures 22D. Pathways such as tracks 74 can be used to electrically couple the horizontal segment in each load structure 22D to signal line 38-1. The port low voltage line 38-1 can, if desired, be formed from the second metal layer 60 of Figure 4 and can receive signals from the drive circuit on screen 14 (for example, the screen drive circuit 20A and / or the door drive circuit 20B of Figure 2).
    [0068] Figure 14 is a side view in cross section of the supplementary load structure 22D of Figure 13 taken along the line.
    Petition 870180069131, of 08/09/2018, p. 10/29
    23/32 line 76 and seen in direction 78. As shown in Figure 14, the polysilicon layer 50 can be located on the buffer layers 66 on the substrate 36. The door insulator 64 can be formed on the buffer layer 66 Door lines G (for example, formed from the metal layer 222 of Figure 4) can be formed on the door insulator 64. The interlayer dielectric layers 206 and the planarization layers 208 and 214 can be formed on the gate lines G. A conductive layer like conductive layer 58 can be formed over planarization layer 214. Conductive layer 58 can be formed from the same layer of transparent conductive material that forms the common electrode layer in pixels 22 ( for example, layer 58 can be formed from the common electrode layer 216 of Figure 4). However, layer 58 does not need to be electrically coupled to the Vcom layer of pixels 22. Instead, layer 58 can be electrically isolated from layer 58 and can be coupled to a ground line (for example, the ground line 38 -2 of Figure 13). A metal layer like the metal layer 60 can be located between the interlayer dielectric layer 206 and the planarization layer 208 and can be used to form the port low voltage line 38-1.
    [0069] Door insulator 64 and dielectric layer 206 may include openings for pathways 74. For example, as shown in Figure 14, layers 64 and 206 include an opening that aligns with polysilicon layer 50 to allow via 74 electrically couple the low voltage line of port 38-1 (ie metal layer 60) to the polysilicon layer 50. This allows the low voltage line of port 38-1 to supply a bias voltage to the polysilicon layer 50.
    [0070] In some arrangements, screen 14 may include an integrated touch sensor. Touch sensor frames can therefore
    Petition 870180069131, of 08/09/2018, p. 10/30
    24/32 example, be integrated into the thin film transistor circuit of the type shown in Figure 4. With this type of arrangement, the common voltage layer on screen 14 can be segmented to support the display and touch functionality. Figure 15 shows an illustrative layout that can be used to implement a segmented Vcom layer to support display and touch functionality. As shown in Figure 15, screen 14 can include conductive Vcom 80 structures, such as rectangular Vcom blocks 80X, which are interconnected using conductive Vcom jumpers 82 to form rows of Vcom (called Vcomr). The jumpers of Vcom 82 (sometimes called XVcom lines) can, for example, be formed from metal layer 210 of Figure 4 or they can be formed from other conductive materials on screen 14. Paths such as pathways 84 can be used to electrically couple lines 82 to Vcomr 80X blocks.
    [0071] Vertical Vcom conductors such as Vcom 80Y columns (called Vcomc) can be interleaved with 80X blocks. The Vcomr and Vcomc conductors of Figure 15 can be formed from tin and indium oxide (for example, layer 216 in Figure 4) or other transparent conductive material and can be used to support display and touch screen functions 14 For example, a time division multiplexing scheme can be used to allow Vcom conductive structures to be used both as ground plane structures for 22 pixels (during display mode operations) and as sensor sensors. touch (during touch sensor mode operations).
    [0072] When pixels 22 of screen 14 are being used to display an image on screen 14, the screen trigger circuit 20A (Figure 2) can, for example, short circuit both the Vcomr 80X and the Vcomc 80Y to a voltage ground as 0 volt or other voltage
    Petition 870180069131, of 08/09/2018, p. 10/314
    25/32 (for example, a fixed reference voltage). In this configuration, the Vcomr 80X and Vcomc 80Y conductors can work together to serve as a part of a common ground plane (conductive plane) for pixels 22 on screen 14. As the Vcomr 80X and Vcomc 80Y are short-circuited in When displaying images in this way, no position-dependent touch data is collected. [0073] At recurring time intervals, the image display functions on screen 14 can be temporarily paused so that touch data can be collected. During these time intervals (sometimes called screen blanking intervals), the screen can operate in touch sensor mode. In touch sensor mode operation, the Vcomr 80X and Vcomc 80Y conductors can be operated independently, so that the position of a touch event can be detected in the X and Y dimensions. There are multiple rows of Vcom (formed from blocks of Vcomr 80X), which allows discrimination of the touch position in relation to the Y dimension. There are also multiple Vcom columns (formed from the Vcomc 80Y), which allows the touch position to be determined in the X dimension .
    [0074] In layouts where screen 14 has an inactive notch area such as notch region 66, there may be rows of door lines (not shown) with fewer pixels than other rows of screen 14 (as discussed in connection with the Figure 7). To avoid variations in brightness that can occur from different door line loading effects, any one or more of the door line loading structures discussed in conjunction with Figures 5 through 14 can be used on screen 14 of Figure 15.
    [0075] In arrangements where touch sensor electrodes are incorporated into the thin film transistor circuit of screen 14, as in the example in Figure 15, the notch region 66 can also interrupt
    Petition 870180069131, of 08/09/2018, p. 10/324
    26/32 per rows of touch sensor electrodes (ie, rows of Vcomr 80X blocks). This creates short rows of Vcomr 80X blocks that have fewer Vcomr 80X blocks than the normal length rows that span the width of the screen substrate 14. If proper care is not taken, XVcom 82 rows in short rows of blocks of Vcomr 80X (for example, the rows of Vcomr 80X blocks on each side of the notch 66) may experience different amounts of load from the XVcom 82 lines in full-width rows of the Vcomr 80X blocks (for example, the rows of the Vcomr 80X blocks) Vcomr 80X below notch 66), which, in turn, can lead to different Vcomr coupling voltages and recovery times when sampling pixel data. This type of pixel data sampling error can lead to different luminance values for pixels in the short rows and pixels in the full width rows, which can cause visible wall effect.
    [0076] To reduce the load mismatch on XVcom 82 lines from screen 14, short rows of Vcomr 80X blocks can be provided with additional charges (sometimes called dummy loads, dummy pixels or overhead port line load structures) ) to help make these rows of Vcomr behave similarly or identically to longer rows of Vcomr on the screen.
    [0077] Figure 16 is a top view of illustrative dummy load structures that can be used in slot region 66 of Figure 15. As shown in Figure 16, screen 14 can include dummy pixels 22D to increase the load on the lines with G port in the groove region 66 (for example, supplementary load structures of the type described in Figures 5 to 14). The dummy pixels 22D can include DE data line extensions and conductive layer 50. DE data line extensions provide capacitive load equal to or similar to G port lines in the inactive region 66 that the DE data lines provide
    Petition 870180069131, of 08/09/2018, p. 10/334
    27/32 to the gate lines G in the active area 40 of the screen 14. Similarly, conductive layer 50 (for example, a polysilicon layer) provides capacitive load equal to or similar to gate lines G in the inactive region 66 that the polysilicon layer 204 (Figure 4) at pixels 22 provides port lines G in the active region 40 of the screen 14.
    [0078] The polysilicon layer 50 in the inactive region 66 can be formed from the same layer of material that forms the polysilicon layer 204 in the active region 40, but the polysilicon layer 50 can be electrically isolated from the polysilicon layer 204. In this way, to supply the appropriate voltage to the polysilicon layer 50, the polysilicon layer can be coupled to a polarizing voltage supply line, such as the low port voltage signal line 38-1 (Vgl). The port low voltage line 38-1 may have vertical segments (for example, segments extending parallel to the y axis of Figure 16) such as the vertical segment 38-1 '. The vertical segments 38-1 'can extend along multiple rows of dummy load structures 22D. Pathways such as tracks 92 can be used to electrically couple the horizontal segment in each load structure 22D to signal line 38-1. The port low voltage line 38-1 can, if desired, be formed from the second metal layer 60 of Figure 4 and can receive signals from the drive circuit on screen 14 (for example, the screen drive circuit 20A and / or the door drive circuit 20B of Figure 2).
    [0079] Additional dummy load structures, sometimes called Vcom row load structures, can be used to increase the load on the XVcom 82 lines in short rows of the Vcomr 80X blocks. Vcom row load structures can include, for example, conductive electrodes 90. Each conductive electrode 90 can overlap a respective block within the blocks of Vcomr 80X. The use of electrodes 90 on the respective blocks of Vcomr 80X
    Petition 870180069131, of 08/09/2018, p. 10/34
    28/32 creates capacitors that increase the capacitive charge on XVcom 82 lines near notch 66 to match or more closely match the capacitive charge on XVcom 82 lines below notch 66. Each capacitor includes a first electrode formed from the conductive layer 90 and a second electrode formed from the Vcomr 80X block. One or more dielectric layers can separate blocks 80X from conductive layer 90. The dielectric material between blocks 80X and conductive layer 90 can be formed from one or more layers of inorganic and / or organic dielectric material on the screen 14. The layer conductive layer 90 can be formed from metal layers, conductive semiconductor layers (e.g., doped polysilicon etc.), or other conductive layers. For example, conductive layer 90 can be formed from conductive layers such as a first layer of door metal, a second layer of door metal, a source drain metal layer, a silicon layer, or other conductive layers the thin film transistor circuit of screen 14.
    [0080] In an illustrative arrangement, which is sometimes described here as an example, conductive electrodes 90 can be formed from the same layer of transparent conductive material that forms pixel electrodes in the active area 40 (for example, conductive electrodes 90 can be formed from the pixel electrode layer 220 of Figure 4). As the electrode 90 is formed from the same layer as the pixel electrode layer 220 of the active area 40, layer 90 is sometimes called an ITO layer. However, electrode 90 does not need to be electrically coupled to the pixel electrodes of pixels 22. Instead, electrodes 90 can be electrically isolated from the pixel ITO of pixels 22. Thus, to provide the proper voltage to conductive layer 90, electrodes 90 can be coupled to a polar voltage supply line
    Petition 870180069131, of 08/09/2018, p. 10/35
    29/32 zation, such as the low voltage signal line (Vgl) 38-1 or ground line 38-2. Routes can be used to couple the respective electrodes 90 to the supply line of suitable polarization voltage (for example, line 38-1 or line 38-2).
    [0081] The capacitor formed from the Vcomr 80X block and the conductive electrode 90 can increase the capacitive charge in the lines of XVcom 82 in the short rows of Vcomr 80X blocks to match or more closely match the capacitive charge in the XVcom 82 lines in the full width rows of the Vcomr 80X blocks. As shown in Figure 16, the Vcom 90 row load structures can be used in combination with door line load structures (for example, polysilicon 50 and DE data line extensions) to reduce luminance differences between rows of short pixels (for example, the rows of pixels from R0 to RM in Figure 7) and rows of full-width pixels (for example, rows RM + 1 and below).
    [0082] If desired, electrodes 90 can also be formed on the portions of the Vcomc column 80Y electrodes that extend into the inactive notch area 66. As the XVcom 82 lines also overlap the Vcomc 80Y electrode portions in the inactive area 66 (see Figure 15), the capacitor formed from the electrodes 90 and the Vcomc 80Y electrodes in the inactive area 66 can be used to further increase the capacitive charge in the lines of XVcom 82 in the short Vcomr rows.
    [0083] According to one modality, a screen is provided that has an active area that emits light and an inactive area that does not emit light, and said screen includes a pixel matrix, screen trigger circuit, coupled data lines to the screen trigger circuit, door lines coupled to the screen trigger circuit, the door lines including a first and a second door line and the first
    Petition 870180069131, of 08/09/2018, p. 10/36
    30/32 the first port line is coupled to fewer pixels than the second port line, with the extra charge structure of the port line increasing the load on the first port line, and a polarizing voltage supply line that polarizes the door line supplementary load structures.
    [0084] According to another modality, the supplementary load structure includes doped polysilicon.
    [0085] According to another modality, the screen includes a transparent conductive layer that overlaps the doped polysilicon.
    [0086] According to another modality, the screen includes a path that electrically couples the conductive layer transparent to the doped polysilicon.
    [0087] According to another modality, the transparent conductive layer is coupled to the polarization voltage supply line.
    [0088] According to another modality, the polarization voltage supply line includes multiple layers of metal.
    [0089] According to another modality, the doped polysilicon has an H shape with two vertical segments connected by a horizontal segment.
    [0090] According to another modality, the track is coupled to the horizontal segment.
    [0091] According to another modality, the two vertical segments overlap the first door line.
    [0092] According to another modality, the pixels include a common voltage layer, and the transparent conductive layer is formed from the same material as the common voltage layer.
    [0093] According to another modality, pixels include transistors with polysilicon channels, and the doped polysilicon is formed from the same material as the polysilicon channels.
    Petition 870180069131, of 08/09/2018, p. 37/104
    31/32 [0094] According to another embodiment, the door lines include a third door line coupled to fewer pixels than the second door line, and the overhead door line load structure increases the load on the third door line. door.
    [0095] According to another modality, some of the data lines overlap the first door line in the inactive area of the screen.
    [0096] According to another modality, the screen includes a metal layer that electrically couples the supplementary load structures from the door line to the polarization voltage supply line.
    [0097] According to another modality, the metal layer is formed from the same material as the data lines.
    [0098] According to one modality, a screen is provided that has an active area and an inactive area, said screen including a matrix of pixels in the active area, the matrix of pixels includes a first and a second row and the the first row has fewer pixels than the second row, port lines coupled to the pixel array, the port lines including a first port row attached to the first pixel row and a second port row attached to the second pixel row, and the first door line has a segment in the inactive area, dummy pixels in the inactive area that do not emit light, and the dummy pixels include doped polysilicon that overlaps the first line of the door line in the inactive area, and a layer of metal that electrically couples the dummy pixels to a polarizing voltage supply line.
    [0099] According to another modality, the screen includes data lines coupled to the pixel matrix, the metal layer is formed from the same material as the data lines.
    [0100] According to another modality, the fictional pixels include extended portions of the data lines.
    [0101] According to one modality, a screen is provided that
    Petition 870180069131, of 08/09/2018, p. 38/104
    32/32 has an active area and an inactive area, the said screen includes an array of pixels in the active area, a common voltage layer includes row electrodes and column electrodes, the common voltage layer is configured to serve as a ground plane for the pixel matrix in a first mode and to collect touch data in a second mode, the rows of signal lines are respectively coupled to the row electrodes, the rows of signal lines include a first and a second signal lines, and the first signal line is coupled to fewer row electrodes than the second signal line, and a conductive layer in the inactive area that overlaps the first signal line to increase the load on the first signal line.
    [0102] According to another modality, the conductive layer includes indium oxide and tin.
    [0103] According to another modality, the screen includes door lines coupled to the pixel array, the door lines including a first and a second door line, the first door line being coupled to fewer pixels than the second door line and the first door line overlap the conductive layer in the idle area, and door line load structures in the idle area of the screen that increase the load on the first door line.
    [0104] According to another modality, the door line load structures include data lines and doped polysilicon that overlap the first door line in the inactive area.
    [0105] The description presented above is merely illustrative, and several modifications can be made by those skilled in the art without deviating from the scope and spirit of the modalities described here. The modalities described above can be implemented individually or in any combination.
    权利要求:
    Claims (20)
    [1]
    1. Screen that has an active area that emits light and an inactive area that does not emit light, characterized by the fact of understanding:
    an array of pixels;
    screen driver circuit;
    data lines coupled to the screen trigger circuit;
    door lines coupled to the screen trigger circuit, the door lines including first and second door lines and the first door line is coupled to fewer pixels than the second door line;
    an overhead door line load structure in the idle area of the screen, the overhead door line load structure increases the load on the first door line; and a polarizing voltage supply line that polarizes the port line overhead load structures.
    [2]
    2. Screen, according to claim 1, characterized by the fact that the supplementary load structure comprises doped polysilicon.
    [3]
    3. Screen according to claim 2, characterized by the fact that it additionally comprises a transparent conductive layer that overlaps the doped polysilicon.
    [4]
    4. Screen, according to claim 3, characterized by the fact that it additionally comprises a path that electrically couples the conductive layer transparent to the doped polysilicon.
    [5]
    5. Screen according to claim 4, characterized by the fact that the transparent conductive layer is coupled to the polarization voltage supply line.
    [6]
    6. Screen according to claim 5, characterized by the fact that the polarization voltage supply line comprises multiple layers of metal.
    Petition 870180069131, of 08/09/2018, p. 10/40
    2/4
    [7]
    7. Screen, according to claim 5, characterized by the fact that the doped polysilicon has an H shape with two vertical segments connected by a horizontal segment.
    [8]
    8. Screen, according to claim 7, characterized by the fact that the track is coupled to the horizontal segment.
    [9]
    9. Screen according to claim 8, characterized by the fact that the two vertical segments overlap the first door line.
    [10]
    10. Screen according to claim 3, characterized by the fact that the pixels comprise a common voltage layer, and the transparent conductive layer is formed from the same material as the common voltage layer.
    [11]
    11. Screen, according to claim 10, characterized by the fact that the pixels comprise transistors with polysilicon channels, and the doped polysilicon is formed from the same material as the polysilicon channels.
    [12]
    12. Screen, according to claim 1, characterized by the fact that the door lines include a third door coupled to fewer pixels than the second door line, with the door line supplementary load structure increasing the load on the third port line.
    [13]
    13. Screen, according to claim 1, characterized by the fact that some of the data lines overlap the first door line in the idle area of the screen.
    [14]
    14. Screen according to claim 1, characterized by the fact that it additionally comprises a metal layer that electrically couples the extra load structures from the door line to the polarization voltage supply line.
    [15]
    15. Screen, according to claim 14, characterized
    Petition 870180069131, of 08/09/2018, p. 41/104
    3/4 due to the fact that the metal layer is formed from the same material as the data lines.
    [16]
    16. Screen that has an active area and an inactive area, characterized by the fact that it comprises:
    a matrix of pixels in the active area, the matrix of pixels including a first and a second row and the first row having fewer pixels than the second row;
    port lines coupled to the pixel array, the port lines including a first port line attached to the first row of pixels and a second port line attached to the second row of pixels, and the first port line having a segment in the inactive area;
    dummy pixels in the inactive area that do not emit light, and the dummy pixels comprise doped polysilicon that overlaps the segment of the first door line in the inactive area; and a layer of metal that electrically couples the dummy pixels to a polarizing voltage supply line.
    [17]
    17. Screen, according to claim 16, characterized by the fact that it additionally comprises data lines coupled to the pixel matrix, the metal layer being formed from the same material as the data lines.
    [18]
    18. Screen, according to claim 17, characterized by the fact that the fictional pixels comprise extended portions of the data lines.
    [19]
    19. Screen that has an active area and an inactive area, characterized by the fact of understanding;
    an array of pixels in the active area;
    a common voltage layer comprising row electrodes and column electrodes, the common voltage layer being configured to serve as a ground plane for the matrix
    Petition 870180069131, of 08/09/2018, p. 42/104
    4/4 pixels in a first mode and to collect touch data in a second mode;
    rows of signal lines respectively coupled to the row electrodes, the rows of signal lines including a first and a second signal line, and the first signal line is coupled to fewer row electrodes than the second signal; and a conductive layer in the inactive area that overlaps the first signal line to increase the load on the first signal line.
    [20]
    20. Screen according to claim 19, characterized in that the conductive layer comprises indium oxide and tin, the screen additionally comprising:
    port lines coupled to the pixel array, the port lines including first and second port lines, the first port line being coupled to fewer pixels than the second port line, and the first port line overlaps with the conductive layer in the inactive area; and door line load structures in the idle area of the screen that increase the load on the first door line, and the door line load structures include data lines and doped polysilicon that overlap the first door line in the area inactive.
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    法律状态:
    2019-03-26| B03A| Publication of a patent application or of a certificate of addition of invention [chapter 3.1 patent gazette]|
    优先权:
    申请号 | 申请日 | 专利标题
    US201762555457P| true| 2017-09-07|2017-09-07|
    US62/555,457|2017-09-07|
    US15/980,437|2018-05-15|
    US15/980,437|US10360862B2|2017-09-07|2018-05-15|Displays with supplemental loading structures|
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